The inventive concept relates to a memory device, a memory system, and a method of clocking data.
Dynamic random access memories (DRAMs) are widely used in numerous applications including in personal computers or servers in computer systems. For high-performance and high-capacity, semiconductor memory devices such as DRAMs are mounted on a memory module, and the memory module is installed in a computer system.
A DRAM which operates in synchronization with a system clock, a clock signal of a system, is known as a synchronous semiconductor memory device (SDRAM). An SDRAM which transmits data in synchronization with rising and falling edges of a system clock signal is known as a double-data-rate (DDR) SDRAM A DDR2 SDRAM and a DDR3 SDRAM having improved operating speeds are successors to a DDR SDRAM. Memory access operations, such as write and read operations, of such semiconductor memory devices are controlled as the semiconductor memory devices communicate with a memory controller. For example, a semiconductor memory device may receive a write command, write data, and a clock signal from a memory controller, and provide read data and a clock signal to the memory controller during a read operation. Such clock signal from the memory controller operates synchronously with the system clock.
FIG. 1 is a block diagram of a conventional semiconductor memory system 10. Referring to FIG. 1, the conventional semiconductor memory system 10 may include a memory controller 11 and a memory module 12 having memory devices MEM1, . . . MEMn. Although one memory module is illustrated in FIG. 1 for convenience of explanation, two or more memory modules may be included in the conventional semiconductor memory system 10.
The memory controller 11 and the memory module 12 transmit and receive signals through various buses located in the conventional semiconductor memory system 10. For example, the memory controller 11 may provide write data to the memory module 12 through a data bus Bus_DQ, or receive data read from the memory module 12 through the data bus Bus_DQ. Also, a clock signal or a data strobe signal may be transmitted between the memory controller 11 and the memory module 12 through other buses located in the conventional memory system 10. For example, a data strobe signal may be transmitted through a strobe bus Bus_strobe, and a system clock signal may be transmitted through a clock bus Bus_S_CLK, as shown in FIG. 1.
Each memory device receives data or a command/address signal provided from the memory controller 11. In general, a memory device receives a data signal in synchronization with a data strobe signal, and receives a command/address signal in synchronization with a system clock signal. When the data signal is received in synchronization with the data strobe signal, as described above, a timing margin may be reduced due to intersymbol interference (ISI) in the data strobe signal. The system clock signal, instead of the data strobe signal, may be used to synchronously receive the data signal without ISI issues, but power consumption increases with more prevalent use of the system clock.